A Low-Noise Low-Power 0.001Hz–1kHz Neural Recording System-on-Chip With Sample-Level Duty-Cycling

This article presents a 16-channel wide-band ultra-low-noise neural recording system-on-chip (SoC) fabricated in 65nm CMOS for chronic use in mobile healthcare settings that spans a bandwidth of 0.001 Hz to 1 kHz through a featured sample-level duty-cycling (SLDC) mode. Each recording channel is implemented by a delta-sigma analog-to-digital converter (ADC) achieving 1.0 $\mu$ V${}_{rms}$ input-referred noise over 1Hz–1kHz bandwidth with a Noise Efficiency Factor (NEF) of 2.93 in continuous operation mode. In SLDC mode, the power supply is duty-cycled while maintaining consistently low input-referred noise levels at ultra-low frequencies (1.1$\mu$V${}_{rms}$ over 0.001Hz–1Hz) and 435 M$\Omega$ input impedance. The functionalities of the proposed SoC are validated with two human electrophysiology applications: recording low-amplitude electroencephalogram (EEG) through electrodes fixated on the forehead to monitor brain waves, and ultra-slow-wave electrogastrogram (EGG) through electrodes fixated on the abdomen to monitor digestion.
Source: IEEE Transactions on Biomedical Circuits and Systems - Category: Biomedical Engineering Source Type: research